// *********************************************************************************/
// Project Name : 
// Author       : huangjunjie
// Email        : 475667558@qq.com
// Creat Time   : 2018/06/07 14:08:51
// File Name    : uart_top.v
// Module Name  : 
// Abstract     : 
//
// CopyRight(c) 2014, Zhimingda digital equipment Co., Ltd.. 
// All Rights Reserved
//
// *********************************************************************************/
//
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//      #### ########  ############             |     Phone: 028-69981523-6172|      
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//
// Modification History:
// 1. initial
// *********************************************************************************/
`timescale 1ns/1ps

module uart_top #(
    parameter   U_DLY               = 1'b1      ,    
    parameter   DAUD_PAR            = 16'd139          
)(
//===================================================================================
// Global  signal 
//===================================================================================
    input                               clk_sys                 ,   
    input                               rst_n                   ,   
//===================================================================================
//
//===================================================================================
    input       [7:0]                   tx_data                 ,   
    input                               tx_start                ,   
    input                               rx                      ,   

    output      [7:0]                   rx_data                 ,   
    output                              rx_dat_val              ,   

    output  reg                         tx_done                 ,   
    output                              tx_busy                 ,   
    output                              tx                         
);
//-----------------------------------------------------------------------------------//
//  Parameter definitions
//-----------------------------------------------------------------------------------//



//-----------------------------------------------------------------------------------//
//  Reg declarations
//-----------------------------------------------------------------------------------//
reg                             tx_busy_dly                         ;   



//-----------------------------------------------------------------------------------//
//  Wire declarations
//-----------------------------------------------------------------------------------//
wire                            baud_en                             ;   
 
wire    [15:0]                  baud_para                           ;   



//-----------------------------------------------------------------------------------//
//  Logic Function
//-----------------------------------------------------------------------------------//

uart_debug_driver u_uart_debug_driver
(
    .rst_n                      (rst_n                      ),
    .clk_uart                   (clk_sys                    ),
    .baud_en                    (baud_en                    ),
    .verify_en                  (1'b0                       ),
    .verify_select              (1'b0                       ),
    .stop_bit_sel               (1'b0                       ),
    .verify_filter              (1'b0                       ),
    .data_width                 (4'h8                       ),
    .tx_data                    (tx_data                    ),
    .tx_start                   (tx_start                   ), 
    .rx_data                    (rx_data                    ),
    .rx_data_vld                (rx_dat_val                 ),
    .tx_busy                    (tx_busy                    ),
    .rx_in                      (rx                         ),
    .tx_out                     (tx                         )
);

uart_debug_baud_gen u_uart_baud_gen(
    .rst_n                      (rst_n                      ),
    .ref_clk                    (clk_sys                    ),
    .period_cnt                 (DAUD_PAR                   ),
    .baud_out                   (baud_en                    )
);


always @(posedge clk_sys or negedge rst_n)
begin
    if(rst_n == 1'b0)
         tx_busy_dly    <= #U_DLY 1'd0;
    else
         tx_busy_dly    <= #U_DLY tx_busy;
end


always @(posedge clk_sys or negedge rst_n)
begin
    if(rst_n == 1'b0)
       tx_done  <= #U_DLY  1'd0;
    else if( ( tx_busy == 1'd0) &&  ( tx_busy_dly == 1'd1))
       tx_done  <= #U_DLY  1'd1;
    else
       tx_done  <= #U_DLY  1'd0;


end

endmodule 




